List of Assemblies  tested in 2001 Test beam
 
 

Modules


 

#

Rad

Sensor

prot.

Chip

thickn.

Supplier

Bonder

Flex

Lab

Bn-10 N SMD Prot-2.0 FEB 250 CIS (?) IZM Flex 2.1 BONN
Bn-12 N SMD Pre-prod FEB 250 TESLA IZM FLEX 2.2 BONN
Bn-13 N SMD Pre-prod FEB 250 CiS IZM FLEX 2.2 BONN
Fh-ge3 N 3289-22 CiS C1c   FEB   CIS AMS FLEX 1 Genoa
Fh-ge4 N 3695-02 SMD CiS   FEB   CiS AMS FLEX 2.2 Genoa
Fh-ge5 N 3696-15 LAD CiS   FEB   CiS AMS FLEX 2.2 Genoa
Fh-ge7 N 3289-04 CiS C1c   FEB   CiS AMS FLEX 2.2 Genoa
Fh-ge6 N CiS 014-12 prep.   FEB   CiS AMS FLEX 2.2 Genoa

Single chips


 

#

Rad

Sensor

prot.

Chip

thickn.

Supplier

Bonder

Lab

OXY4 3.0*10**14       FEB CiS AMS Genoa
OXY5 5.0*10**14       FEB CiS AMS Genoa
OXY6 1.1*10**15       FEB CiS AMS Genoa
geb15 (oxy) 1.0*10**15       FEB CiS AMS Genoa
OXY1 5.6*10**14       FEB CiS AMS Genoa
NOTOXY1 3.2*10**14       FEB CiS AMS Genoa
OXY2 3.2*10**14       FEB CiS AMS Genoa
OXY3 3.2*10**14       FEB CiS AMS Genoa
Geb13 No (?) SSG     FEB CiS AMS Genoa
Ge_D_3 No   preprod   FED CiS AMS Genoa
Ge_D_4 No   preprod   FED CiS AMS Genoa
Bn_D(2S)_1 No   prot 1   FED CiS ? IZM BONN
Bn_D(2S)_2 No   prot 1   FED CiS ? IZM BONN
Bn_D(2S)_3 No   prot 1   FED CiS ? IZM BONN
BONN DIAMOND No       FEC CiS ? IZM ? BONN - private
CPPM_Tesla_D or Ma1_FED before and after   preprod   FED Tesla IZM Milano




ATLAS Pixels H8 Run Summary
September - October 2001








 

R
U
N
#

E
V
T
S

 B 

PLL1 DEVICE / CONFIG FILE

V bias

I leak [µA]

D
V
D
D

X POS
[mm]

Y POS
[mm]

 D 
 E 
 L 
 A 
 Y 

PLL2 DEVICE / CONFIG FILE

 P 
 H 
 I 

 T 
 H 
 E 
 T 
 A 

V bias

I leak [µA]

D
V
D
D

X POS
[mm]

Y POS
[mm]

 D 
 E 
 L 
 A 
 Y 

Comments

1074 1M 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150     48.25 10.72 66
 
                Narrow beam centered on chip 3
1075 500k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150     39.15 14.2 66
 
                Narrow beam centered on chips 4-11
1077 2M 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150     31.55 12.2 66
 
                Narrow beam centered on chips 5-10
1078 200k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG_chip7
150 11   23.95 12.2 66
 
                Normal (wide) beam on chip 7
1079 200k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG_chip7
150 11   23.95 12.2 66
 
                Normal (wide) beam on chip 7
1080 1M 0
 
           
Ma-D-5
20MRad
0 0 300 25   18 11.25 75  
1081 500k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150 7.6 3.1 24 12.7 66
 
                Chip 9
1083 200k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150 7.6 3.1 56.4 15.2 66
 
                Chip 13
1084 200k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150 7.6 5.1 64.0 15.2 66
 
                Chip 14
1085 200k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150 7.5 3.1 71.6 15.2 66
Ma-D-5
ma5_fed
15 0 300 24.5   18 11.25 75 Dual readout now ok again; PLL1 chip 15
1087 200k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150 7.5 3.1 74.6 7.2 66
Ma-D-5
ma5_fed
15 0 300 23.8   16 11.25 75 PLL1 chip 0
1088 200k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150 7.3 3.1 65.4 5.2 66
Ma-D-5
ma5_fed
15 0 300 24.0   16 11.25 75 PLL1 chip 1
1090 200k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150 7.8 3.1 57.8 5.2 66
Ma-D-5
ma5_fed
15 0 300 24   16 11.25 75 PLL1 chip 2
1092 200k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150 7.3 8.1 25.4 5.7 66
Ma-D-5
ma5_fed
15 0 300 24   16 11.25 75 PLL1 chip 6; shoul have been 27.4mm ideally for PLL1
1093 200k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150 7.4 3.1 27.2 5.7 66
Ma-D-5
ma5_fed
30 0 300 23.8   16 11.25 75 PLL1 chip 6
1095 300k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150 7.4 3.1 19.8 5.7 66
Ma-D-5
ma5_fed
30 0 300 22.8 3.5 13 11.25 75 PLL1 chip 7
1096 500k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150 7.3 3.1 35 5.7 66
Ma-D-5
ma5_fed
30 0 600 33.1 3.5 13 11.25 75 PLL1 chip 5
1097 500k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150 7.0 3.1 42.6 5.7 66
Ma-D-5
ma5_fed
35 0 500 33.0 3.5 13 11.25 75 PLL1 chip 4
1098 400k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150 7.0 3.1 50.2 5.7 66
Ma-D-5
ma5_fed
30 0 400 26.7 3.5 13 11.25 75 PLL1 chip 3
1099 110k 0
Bn-12
bn_mod12_THB1_SID_sTDAC_noG
150 6.9 3.1 57.8 5.7 66
Ma-D-5
ma5_fed
30 0 200 28.1 3.5 13 11.25 75 PLL1 chip 2

R
U
N
#

E
V
T
S

 B 

PLL1 DEVICE / CONFIG FILE

V bias

I leak [µA]

D
V
D
D

X POS
[mm]

Y POS
[mm]

 D 
 E 
 L 
 A 
 Y 

PLL2 DEVICE / CONFIG FILE

 P 
 H 
 I 

 T 
 H 
 E 
 T 
 A 

V bias

I leak [µA]

D
V
D
D

X POS
[mm]

Y POS
[mm]

 D 
 E 
 L 
 A 
 Y 

Comments

1105 400k 0
 
           
Ma-D-5
ma5_fed
30 0 200 17.0 3.5 13 11.25 75 PLL1 has problems (too many empty evts)
1106 500k 0
 
           
Ma-D-5
ma5_fed
30 0 150 14.0 3.5 13 11.25 75  
1107 300k 0
 
           
Ma-D-5
ma5_fed
30 0 550 28.6 3.5 13 11.25 75  
1108 200k 0
 
           
Ma-D-5
ma5_fed
30 0 550 28.3 3.5 13 11.25 75  
1109 200k 0
 
           
Ma-D-5
ma5_fed
30 0 450 25.3 3.5 13 11.25 75  
1110 300k 0
 
           
Ma-D-5
ma5_fed
30 0 450 25.3 3.5 13 11.25 75  
1111 500k 0
 
           
Ma-D-5
ma5_fed
30 0 350 22.1 3.5 13 11.25 75  
1112 500k 0
 
           
Ma-D-5
ma5_fed
15 0 600 28.3 3.5 16 11.25 75  
1113 1M 0
 
           
Ma-D-5
ma5_fed
0 0 600 27.3 3.5 18 11.25 75  
1114 1M 0
 
           
ge-d4
ged4_fed
0 0 300 118 3.68 18 12.0 75  
1115 1M 0
 
           
ge-d4
ged4_fed
15 0 300 120 3.68 18 12.0 75  
1116 500k 0
 
           
ge-d4
ged4_fed
30 0 300 123 3.68 24 12.0 75  
1117 500k 0
 
           
ge-d4
ged4_fed
30 0 500 244 3.68 24 12.0 75  
1118 500k 0
 
           
ge-d4
ged4_fed
30 0 600 319 3.68 24 12.0 75  
1119 500k 0
 
           
ge-d4
ged4_fed
30 0 400 184 3.68 24 12.0 75  
1120 500k 0
 
           
ge-d4
ged4_fed
30 0 200 69.9 3.68 24 12.0 75  
1121 500k 0
 
           
ge-d4
ged4_fed
30 0 150 45.3 3.68 24 12.0 75  
1122 500k 0
 
           
ge-d4
ged4_fed
30 0 550 280 3.68 24 12.0 75  
1123 500k 0
 
           
ge-d4
ged4_fed
30 0 450 217 3.68 24 12.0 75  
1124 500k 0
 
           
ge-d4
ged4_fed
30 0 350 154 3.68 24 12.0 75  
1126 1M 0
 
           
ge-d3
ge_d_3_10M
0 0 300 75 3.5 21 9 75 PT100=100.8 Ohm
1127 1M 0
 
           
ge-d3
ge_d_3_10M
0 0 300 71 3.5 21 9 75 PT100=99.7 Ohm

R
U
N
#

E
V
T
S

 B 

PLL1 DEVICE / CONFIG FILE

V bias

I leak [µA]

D
V
D
D

X POS
[mm]

Y POS
[mm]

 D 
 E 
 L 
 A 
 Y 

PLL2 DEVICE / CONFIG FILE

 P 
 H 
 I 

 T 
 H 
 E 
 T 
 A 

V bias

I leak [µA]

D
V
D
D

X POS
[mm]

Y POS
[mm]

 D 
 E 
 L 
 A 
 Y 

Comments

1128 1M 0
 
           
ge-d3
ge_d_3_10M
0 0 300 71 3.5 21 9 75  
1129 1M 0
 
           
ge-d3
ge_d_3_10M
0 0 300 71 3.5 21 9 75  
1132 500k  
 
           
ge-d3
ge_d_3_10M
15 0 300 71 3.5 21 9 75  
1133 500k  
 
           
ge-d3
ge_d_3_10M
30 0 150 25.5 3.5 26 9 75 PT100=99.9 Ohm
1134 500k  
 
           
ge-d3
ge_d_3_10M
30 0 200 36.9 3.5 29 9 75 PT100=99.9 Ohm
1135 500k  
 
           
ge-d3
ge_d_3_10M
30 0 300 71.45 3.5 26 9 75 PT100=99.9 Ohm
1136 500k  
 
           
ge-d3
ge_d_3_10M
30 0 400 120 3.5 26 9 75 PT100=100.0 Ohm
1137 500k  
 
           
ge-d3
ge_d_3_10M
30 0 500 174 3.5 26 9 75 PT100=100.0 Ohm
1138 500k  
 
           
ge-d3
ge_d_3_10M
30 0 600 236 3.5 26 9 75 PT100=100.0 Ohm
1139 250K  
 
           
ge-d3
ge_d_3_10M
30 0 550 205 3.5 26 9 75 PT100=100.0 Ohm
1140 250K  
 
           
ge-d3
ge_d_3_10M
30 0 450 148 3.5 26 9 75 PT100=99.9 Ohm
1141 250K  
 
           
ge-d3
ge_d_3_10M
30 0 350 97 3.5 26 9 75 PT100=99 Ohm
1142 250K  
 
           
ge-d3
ge_d_3_10M
30 0 250 54 3.5 26 9 75 PT100=99 Ohm







ATLAS PIXEL Testbeam Analysis Home Page

 

ATLAS Milano Testbeam Page


Author: Fabio Manca